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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog/] [tb_ethernet.v] - Rev 266

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Rev Log message Author Age Path
266 Flow control test almost finished. mohor 7952d 18h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7953d 09h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7953d 21h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7955d 15h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7955d 17h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7960d 22h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7987d 18h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7987d 21h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7996d 22h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 8015d 21h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 8017d 17h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 8019d 17h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 8019d 20h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 8022d 16h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 8022d 16h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 8022d 16h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 8022d 20h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 8022d 23h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8022d 23h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 8027d 19h /ethmac/tags/rel_27/bench/verilog/tb_ethernet.v

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