URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk] - Rev 13

Rev	Log message	Author	Age	Path
13	Fixed some synthesis warnings.	rherveille	8373d 14h	/i2c/trunk
12	no message	rherveille	8379d 06h	/i2c/trunk
11	Changed RST_LVL define to parameter.	rherveille	8382d 13h	/i2c/trunk
10	Created new directory structure. Added Verilog version.	rherveille	8404d 10h	/i2c/trunk
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8474d 05h	/i2c/trunk
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8474d 05h	/i2c/trunk
7	added some remarks, fixed some sensitivity lists	rherveille	8543d 08h	/i2c/trunk
6	fixed typo txt -> txr	rherveille	8547d 11h	/i2c/trunk
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8554d 10h	/i2c/trunk
4	WISHBONE I2C Master Core: initial release	rherveille	8606d 13h	/i2c/trunk
2	initial release	rherveille	8668d 12h	/i2c/trunk
1	Standard project directories initialized by cvs2svn.		8668d 12h	/i2c/trunk