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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_immu_tlb.v] - Rev 1765

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1765 root 5744d 21h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
1164 This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'. 7849d 17h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
1079 RAMs wrong connected to the BIST scan chain. mohor 8070d 04h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8081d 00h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8145d 14h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8329d 16h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8343d 19h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8368d 12h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_immu_tlb.v

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