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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [fifo_b/] [bench_fifo_b.vf] - Rev 22

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22 Created separate module-level environments for fifo_b
and scoreboard. Added some documentation on the
example bridge, including a PDF preso giving a basic
introduction to ethernet.
ghutchis 5424d 09h /srdydrdy_lib/trunk/env/verilog/fifo_b/bench_fifo_b.vf
6 Modified "B" output buffer for full-rate operation ghutchis 5440d 14h /bench_fifo_b.vf

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