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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Rev 48

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48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8334d 01h /uart16550/trunk/rtl/verilog/uart_regs.v
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8339d 03h /uart16550/trunk/rtl/verilog/uart_regs.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8341d 01h /uart16550/trunk/rtl/verilog/uart_regs.v
44 fixed more typo bugs gorban 8355d 00h /uart16550/trunk/rtl/verilog/uart_regs.v
43 lsr1r error fixed. mohor 8355d 07h /uart16550/trunk/rtl/verilog/uart_regs.v
42 ti_int_pnd error fixed. mohor 8355d 07h /uart16550/trunk/rtl/verilog/uart_regs.v
41 ti_int_d error fixed. mohor 8355d 08h /uart16550/trunk/rtl/verilog/uart_regs.v
40 Synthesis bugs fixed. Some other minor changes gorban 8357d 10h /uart16550/trunk/rtl/verilog/uart_regs.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8359d 08h /uart16550/trunk/rtl/verilog/uart_regs.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8360d 05h /uart16550/trunk/rtl/verilog/uart_regs.v
36 no message mohor 8365d 13h /uart16550/trunk/rtl/verilog/uart_regs.v
35 Fixes to break and timeout conditions gorban 8367d 07h /uart16550/trunk/rtl/verilog/uart_regs.v
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8369d 05h /uart16550/trunk/rtl/verilog/uart_regs.v
33 Small synopsis fixes gorban 8378d 12h /uart16550/trunk/rtl/verilog/uart_regs.v
32 Changes data_out to be synchronous again as it should have been. gorban 8379d 06h /uart16550/trunk/rtl/verilog/uart_regs.v
31 small fix gorban 8380d 02h /uart16550/trunk/rtl/verilog/uart_regs.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8435d 01h /uart16550/trunk/rtl/verilog/uart_regs.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8436d 06h /uart16550/trunk/rtl/verilog/uart_regs.v

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