URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_top.v] - Rev 48

Rev	Log message	Author	Age	Path
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8334d 00h	/uart16550/trunk/rtl/verilog/uart_top.v
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8360d 04h	/uart16550/trunk/rtl/verilog/uart_top.v
33	Small synopsis fixes	gorban	8378d 12h	/uart16550/trunk/rtl/verilog/uart_top.v
30	Modified port names again	gorban	8434d 06h	/uart16550/trunk/rtl/verilog/uart_top.v
29	Things connected to parity changed. Clock devider changed.	mohor	8435d 00h	/uart16550/trunk/rtl/verilog/uart_top.v
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8436d 05h	/uart16550/trunk/rtl/verilog/uart_top.v