URL https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk

Subversion Repositories uart_fifo_cpu_if_sv_testbench

[/] [uart_fifo_cpu_if_sv_testbench/] [trunk/] [sim] - Rev 2

Rev	Log message	Author	Age	Path
2	Added complete UART RTL and testbench. Both compile, but not debugged in simulator yet. Synchronous FIFO yet to be added. File headers need tidying.	andrewbridger	5016d 02h	/uart_fifo_cpu_if_sv_testbench/trunk/sim