OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1362

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1362 initialise dev_mem->chip_select in register_memory nogj 7161d 01h /
1361 Cleanup test peripheral nogj 7161d 01h /
1360 Add dynamic hooks to sim_reset nogj 7161d 01h /
1359 Pass private data in readfunc/writefunc callbacks nogj 7161d 01h /
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7161d 01h /
1357 This commit was manufactured by cvs2svn to create tag 'stable_0_1_0'. 7168d 12h /
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7168d 12h /
1355 Fix dmatest testcase nogj 7168d 12h /
1354 typing fixes phoenix 7169d 07h /
1353 Modularise simulator command parsing nogj 7170d 04h /
1352 Optimise execution history tracking nogj 7170d 04h /
1351 Reindent create_watchpoints useing a more compact indentation style nogj 7170d 04h /
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7170d 05h /
1349 Works with GDB jcastillo 7172d 04h /
1348 Converted to current simulator configuration format jcastillo 7175d 09h /
1347 Remove backup file nogj 7181d 15h /
1346 Remove the global op structure nogj 7183d 08h /
1345 Fix out-of-tree builds nogj 7183d 08h /
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7183d 08h /
1343 * Fix warnings in insnset.c and execute.c nogj 7183d 09h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.