URL https://opencores.org/ocsvn/ourisc/ourisc/trunk

Subversion Repositories ourisc

[/] - Rev 10

Rev	Log message	Author	Age	Path
10	Non synthetizable memory used for simulation issues.	joaocarlos	4047d 14h	/
9	Fix port names and header.	joaocarlos	4047d 14h	/
8	Fix header.	joaocarlos	4047d 14h	/
7	Program counter.	joaocarlos	4047d 15h	/
6	Fix coding sintax.	joaocarlos	4047d 15h	/
5	uRISC predefined processor flags.	joaocarlos	4075d 16h	/
4	Basic uRISC instruction set opcodes.	joaocarlos	4075d 16h	/
3	missing and should wasn't to be commited iet.	joaocarlos	4075d 16h	/
2	Common primitive processor components.	joaocarlos	4075d 16h	/
1	The project and the structure was created	root	4080d 21h	/