OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] - Rev 68

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 add instruction cache and DELAY parameters for external ram, rom simont 7982d 05h /8051/tags/rel_19/
67 add parameters for instruction cache simont 7982d 05h /8051/tags/rel_19/
66 added xrom_test simont 7983d 02h /8051/tags/rel_19/
65 add oc8051_icache and oc8051_cache_ram simont 7983d 02h /8051/tags/rel_19/
64 signal es_int=1'b0 simont 7983d 02h /8051/tags/rel_19/
63 initial import simont 7983d 02h /8051/tags/rel_19/
62 fix bugs in instruction interface simont 7983d 02h /8051/tags/rel_19/
61 fix bug simont 7984d 04h /8051/tags/rel_19/
60 initial inport simont 7985d 05h /8051/tags/rel_19/
59 add external rom simont 7989d 00h /8051/tags/rel_19/
58 add external rom testing simont 7989d 00h /8051/tags/rel_19/
57 add module oc8051_xrom simont 7989d 00h /8051/tags/rel_19/
56 initial CVS input simont 7989d 00h /8051/tags/rel_19/
55 added parameter DELAY simont 7989d 00h /8051/tags/rel_19/
54 cahnge interface to instruction rom simont 7989d 00h /8051/tags/rel_19/
53 initial CVS inport simont 7989d 00h /8051/tags/rel_19/
52 fix bugs simont 7989d 00h /8051/tags/rel_19/
51 fix bugs simont 7991d 05h /8051/tags/rel_19/
50 fix bugs simont 7991d 06h /8051/tags/rel_19/
49 verification added simont 7998d 05h /8051/tags/rel_19/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.