URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] - Rev 86

Rev	Log message	Author	Age	Path
86	initial input	simont	7919d 19h	/8051/trunk/
85	prepare bugs	simont	7919d 20h	/8051/trunk/
84	remove wb_bus_mon	simont	7927d 19h	/8051/trunk/
83	replace some modules	simont	7927d 19h	/8051/trunk/
82	replace some modules	simont	7927d 19h	/8051/trunk/
81	initial import	simont	7927d 19h	/8051/trunk/
80	removing unused modules	simont	7927d 19h	/8051/trunk/
79	initial import	simont	7927d 19h	/8051/trunk/
78	alu with registered outputs	simont	7987d 19h	/8051/trunk/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7996d 16h	/8051/trunk/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7996d 16h	/8051/trunk/
75	initial import	simont	7996d 16h	/8051/trunk/
74	add module oc8051_wb_iinterface	simont	8004d 16h	/8051/trunk/
73	initial import	simont	8004d 16h	/8051/trunk/
72	fix bug in interface to external data ram	simont	8004d 18h	/8051/trunk/
71	add cache	simont	8008d 18h	/8051/trunk/
70	initial import	simont	8008d 18h	/8051/trunk/
69	add parameters	simont	8008d 20h	/8051/trunk/
68	add instruction cache and DELAY parameters for external ram, rom	simont	8008d 20h	/8051/trunk/
67	add parameters for instruction cache	simont	8008d 20h	/8051/trunk/