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[/] [ethmac/] [tags/] [rel_25/] [rtl/] [verilog/] - Rev 226

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Rev	Log message	Author	Age	Path
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7987d 19h	/ethmac/tags/rel_25/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7991d 19h	/ethmac/tags/rel_25/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7994d 19h	/ethmac/tags/rel_25/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	7994d 21h	/ethmac/tags/rel_25/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7995d 18h	/ethmac/tags/rel_25/rtl/verilog/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7995d 18h	/ethmac/tags/rel_25/rtl/verilog/
212	Minor $display change.	mohor	7995d 18h	/ethmac/tags/rel_25/rtl/verilog/
211	Bist added.	mohor	7995d 18h	/ethmac/tags/rel_25/rtl/verilog/
210	BIST added.	mohor	7995d 18h	/ethmac/tags/rel_25/rtl/verilog/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	8012d 17h	/ethmac/tags/rel_25/rtl/verilog/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	8012d 17h	/ethmac/tags/rel_25/rtl/verilog/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	8015d 18h	/ethmac/tags/rel_25/rtl/verilog/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	8023d 20h	/ethmac/tags/rel_25/rtl/verilog/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	8024d 21h	/ethmac/tags/rel_25/rtl/verilog/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	8025d 21h	/ethmac/tags/rel_25/rtl/verilog/
165	HASH improvement needed.	mohor	8026d 00h	/ethmac/tags/rel_25/rtl/verilog/
164	Ethernet debug registers removed.	mohor	8026d 00h	/ethmac/tags/rel_25/rtl/verilog/
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	8026d 22h	/ethmac/tags/rel_25/rtl/verilog/
160	error acknowledge cycle termination added to display.	mohor	8026d 22h	/ethmac/tags/rel_25/rtl/verilog/
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	8027d 18h	/ethmac/tags/rel_25/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_25/] [rtl/] [verilog/] - Rev 226

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