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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 65

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Rev Log message Author Age Path
65 -update dfdiv / dfmul robfinch 949d 02h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 949d 02h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 949d 15h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 949d 16h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 949d 21h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1211d 02h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1352d 14h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1377d 15h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization		 robfinch 1378d 07h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1378d 21h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1380d 01h /ft816float/trunk/rtl/verilog2/
51 - got rid of 'DF0' robfinch 1380d 04h /ft816float/trunk/rtl/verilog2/
50 - added decimal floating-point adder robfinch 1380d 12h /ft816float/trunk/rtl/verilog2/
49 - pipelining robfinch 1400d 16h /ft816float/trunk/rtl/verilog2/
48 - refactoring to use packages robfinch 1425d 00h /ft816float/trunk/rtl/verilog2/
35 - additional pipelining in divider
- radix4 primitive		 robfinch 1640d 15h /ft816float/trunk/rtl/verilog2/
34 - add pipeline stage in divider robfinch 1640d 18h /ft816float/trunk/rtl/verilog2/
33 - mult114 for FMA robfinch 1893d 02h /ft816float/trunk/rtl/verilog2/
32 - FMA, test bench for FMA robfinch 1893d 02h /ft816float/trunk/rtl/verilog2/
31 - preserve nan sign in addsub robfinch 1893d 14h /ft816float/trunk/rtl/verilog2/

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