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[/] [ion/] [trunk/] - Rev 134

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Rev Log message Author Age Path
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4867d 11h /ion/trunk/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4870d 09h /ion/trunk/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4870d 09h /ion/trunk/
131 change to local system-dependent directory path ja_rd 4870d 09h /ion/trunk/
130 typo fix ja_rd 4870d 09h /ion/trunk/
129 updated pregenerated demo ('hello') ja_rd 4870d 09h /ion/trunk/
128 updated precompiled simulation testbench ja_rd 4870d 09h /ion/trunk/
127 added SDRAM verilog simulation model to sim script ja_rd 4870d 09h /ion/trunk/
126 added SDRAM verilog simulation model ja_rd 4870d 09h /ion/trunk/
125 MPU templates now use the real cache by default ja_rd 4870d 09h /ion/trunk/
124 Fixed typo in python script header comment ja_rd 4915d 15h /ion/trunk/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4915d 18h /ion/trunk/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4915d 18h /ion/trunk/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4916d 09h /ion/trunk/
120 Updated main package with lots of wait states for all areas ja_rd 4925d 12h /ion/trunk/
119 Updated pre-generated simulation and synthesis demos ja_rd 4925d 12h /ion/trunk/
118 Updates sim scripts to include new cache ja_rd 4925d 12h /ion/trunk/
117 Updated project doc (still not fully up to date) ja_rd 4925d 12h /ion/trunk/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic		 ja_rd 4925d 13h /ion/trunk/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)		 ja_rd 4925d 15h /ion/trunk/

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