OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] - Rev 870

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
870 Added defines for enabling generic FF based memory macro for register file. lampret 8147d 08h /or1k/trunk/or1200/rtl/
869 Added generic flip-flop based memory macro instantiation. lampret 8147d 08h /or1k/trunk/or1200/rtl/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8218d 08h /or1k/trunk/or1200/rtl/
794 Added again just recently removed full_case directive lampret 8218d 08h /or1k/trunk/or1200/rtl/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8218d 08h /or1k/trunk/or1200/rtl/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8218d 08h /or1k/trunk/or1200/rtl/
788 Some of the warnings fixed. lampret 8218d 09h /or1k/trunk/or1200/rtl/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8219d 05h /or1k/trunk/or1200/rtl/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8219d 05h /or1k/trunk/or1200/rtl/
776 Updated defines. lampret 8219d 05h /or1k/trunk/or1200/rtl/
775 Optimized cache controller FSM. lampret 8219d 06h /or1k/trunk/or1200/rtl/
774 Removed old files. lampret 8219d 06h /or1k/trunk/or1200/rtl/
737 Added alternative for critical path in DU. lampret 8234d 00h /or1k/trunk/or1200/rtl/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8236d 23h /or1k/trunk/or1200/rtl/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8236d 23h /or1k/trunk/or1200/rtl/
668 Lapsus fixed. simons 8261d 09h /or1k/trunk/or1200/rtl/
663 No longer using async rst as sync reset for the counter. lampret 8263d 23h /or1k/trunk/or1200/rtl/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8264d 20h /or1k/trunk/or1200/rtl/
636 Fixed combinational loops. lampret 8274d 05h /or1k/trunk/or1200/rtl/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8278d 23h /or1k/trunk/or1200/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.