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[/] [pci/] [tags/] [rel_10/] - Rev 76

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Rev Log message Author Age Path
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7917d 00h /pci/tags/rel_10/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7920d 01h /pci/tags/rel_10/
73 Bug fixes, testcases added. mihad 7920d 01h /pci/tags/rel_10/
72 *** empty log message *** mihad 7967d 05h /pci/tags/rel_10/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7974d 21h /pci/tags/rel_10/
69 Changed BIST signal names etc.. mihad 8012d 05h /pci/tags/rel_10/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8015d 14h /pci/tags/rel_10/
67 Changed BIST signals for RAMs. tadejm 8015d 19h /pci/tags/rel_10/
66 Changed empty status generation in pciw_fifo_control.v mihad 8019d 05h /pci/tags/rel_10/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8022d 03h /pci/tags/rel_10/
64 The testcase I just added in previous revision repaired mihad 8022d 06h /pci/tags/rel_10/
63 Added additional testcase and changed rst name in BIST to trst mihad 8022d 07h /pci/tags/rel_10/
62 Added BIST signals for RAMs. mihad 8025d 00h /pci/tags/rel_10/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8033d 00h /pci/tags/rel_10/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8033d 02h /pci/tags/rel_10/
58 Removed all logic from asynchronous reset network mihad 8038d 02h /pci/tags/rel_10/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8038d 08h /pci/tags/rel_10/
56 Number of state bits define was removed mihad 8038d 22h /pci/tags/rel_10/
55 Changed state machine encoding to true one-hot mihad 8038d 23h /pci/tags/rel_10/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8072d 01h /pci/tags/rel_10/

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