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[/] [pci/] [tags/] [rel_12/] - Rev 77

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Rev	Log message	Author	Age	Path
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7913d 19h	/pci/tags/rel_12/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7916d 19h	/pci/tags/rel_12/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7919d 20h	/pci/tags/rel_12/
73	Bug fixes, testcases added.	mihad	7919d 20h	/pci/tags/rel_12/
72	* empty log message *	mihad	7967d 00h	/pci/tags/rel_12/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7974d 16h	/pci/tags/rel_12/
69	Changed BIST signal names etc..	mihad	8011d 23h	/pci/tags/rel_12/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8015d 09h	/pci/tags/rel_12/
67	Changed BIST signals for RAMs.	tadejm	8015d 13h	/pci/tags/rel_12/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8019d 00h	/pci/tags/rel_12/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8021d 22h	/pci/tags/rel_12/
64	The testcase I just added in previous revision repaired	mihad	8022d 00h	/pci/tags/rel_12/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8022d 02h	/pci/tags/rel_12/
62	Added BIST signals for RAMs.	mihad	8024d 19h	/pci/tags/rel_12/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8032d 19h	/pci/tags/rel_12/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8032d 20h	/pci/tags/rel_12/
58	Removed all logic from asynchronous reset network	mihad	8037d 20h	/pci/tags/rel_12/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8038d 02h	/pci/tags/rel_12/
56	Number of state bits define was removed	mihad	8038d 17h	/pci/tags/rel_12/
55	Changed state machine encoding to true one-hot	mihad	8038d 18h	/pci/tags/rel_12/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] - Rev 77

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