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[/] [pci/] [tags/] [rel_12/] - Rev 88

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Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7855d 22h /pci/tags/rel_12/
87 Updated acording to RTL changes. mihad 7867d 19h /pci/tags/rel_12/
86 Entered the option to disable no response counter in wb master. mihad 7867d 19h /pci/tags/rel_12/
85 Changed Vendor ID defines. mihad 7868d 00h /pci/tags/rel_12/
84 Changed vendor ID. mihad 7871d 18h /pci/tags/rel_12/
83 Cleaned up the code. No functional changes. mihad 7896d 16h /pci/tags/rel_12/
81 Updated synchronization in top level fifo modules. mihad 7910d 13h /pci/tags/rel_12/
79 Updated. mihad 7913d 18h /pci/tags/rel_12/
78 Old files with wrong names removed. mihad 7913d 18h /pci/tags/rel_12/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7913d 18h /pci/tags/rel_12/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7916d 18h /pci/tags/rel_12/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7919d 18h /pci/tags/rel_12/
73 Bug fixes, testcases added. mihad 7919d 19h /pci/tags/rel_12/
72 *** empty log message *** mihad 7966d 22h /pci/tags/rel_12/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7974d 14h /pci/tags/rel_12/
69 Changed BIST signal names etc.. mihad 8011d 22h /pci/tags/rel_12/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8015d 07h /pci/tags/rel_12/
67 Changed BIST signals for RAMs. tadejm 8015d 12h /pci/tags/rel_12/
66 Changed empty status generation in pciw_fifo_control.v mihad 8018d 22h /pci/tags/rel_12/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8021d 21h /pci/tags/rel_12/

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