OpenCores
URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] - Rev 124

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
124 Assigned UART signals to ports on top-level entity trinklhar 6455d 13h /rise/trunk/
123 Removed UART again trinklhar 6455d 14h /rise/trunk/
122 Removed UART again again trinklhar 6455d 14h /rise/trunk/
121 Added address constants for uart access (memory mapped I/O) trinklhar 6455d 15h /rise/trunk/
120 Added UART module to memory entity trinklhar 6455d 15h /rise/trunk/
119 Uart wieder ausgebaut trinklhar 6456d 10h /rise/trunk/
118 insert Uart address constant trinklhar 6456d 10h /rise/trunk/
117 Uart im mem_stage trinklhar 6456d 10h /rise/trunk/
116 writes to uart when write to reg 0 trinklhar 6457d 16h /rise/trunk/
115 *** empty log message *** trinklhar 6458d 06h /rise/trunk/
114 Uart 0.3 trinklhar 6459d 10h /rise/trunk/
113 Uart reset funkt trinklhar 6459d 11h /rise/trunk/
112 Uart drin aber signale nicht eingebunden trinklhar 6459d 13h /rise/trunk/
111 - Fixed bug where certain opcodes did not check for availability of
registers.		 cwalter 6462d 04h /rise/trunk/
110 - Added missing file to CVS. cwalter 6462d 11h /rise/trunk/
109 - Assembler code for ST produced wrong instruction format. cwalter 6463d 03h /rise/trunk/
108 no message cwalter 6463d 03h /rise/trunk/
107 - Added new example for memory testing. cwalter 6463d 03h /rise/trunk/
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6463d 03h /rise/trunk/
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6463d 03h /rise/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.