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[/] [socgen/] - Rev 88

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Rev Log message Author Age Path
88 added xml files for test benches
added gEDA sym sch starter templates		 jt_eaton 4922d 06h /socgen/
87 removed prebuilt geda schematics and symbols jt_eaton 4932d 23h /socgen/
86 split out all fpgas into families
added fpga pad_ring level		 jt_eaton 4940d 20h /socgen/
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines		 jt_eaton 4947d 19h /socgen/
84 removed unneeded files jt_eaton 4998d 00h /socgen/
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4998d 04h /socgen/
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 5012d 22h /socgen/
81 morphing xml files to use 1685
removed log directories		 jt_eaton 5034d 05h /socgen/
80 now generate all sims and syns param and filelists for xml jt_eaton 5063d 20h /socgen/
79 removed unsupported code jt_eaton 5070d 00h /socgen/
78 removed unsupported fpga jt_eaton 5070d 00h /socgen/
77 now generate syn and cov Makefiles
leave log and out files in sim/run directory		 jt_eaton 5070d 01h /socgen/
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory		 jt_eaton 5072d 06h /socgen/
75 added linting using verilator jt_eaton 5075d 22h /socgen/
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5081d 04h /socgen/
73 removed dup png files jt_eaton 5089d 03h /socgen/
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog		 jt_eaton 5089d 05h /socgen/
71 ignore anything in work jt_eaton 5095d 22h /socgen/
70 ignore work jt_eaton 5095d 22h /socgen/
69 added work dir jt_eaton 5095d 22h /socgen/

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