URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] [storm_core/] - Rev 15

Rev	Log message	Author	Age	Path
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4631d 07h	/storm_core/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4769d 03h	/storm_core/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4769d 23h	/storm_core/
12	- corrected error in memory write back interface - corrected immediate/register offset for byte/halfword memory access	zero_gravity	4770d 04h	/storm_core/
11		zero_gravity	4773d 08h	/storm_core/
10	New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface. Ready to execute assembled ARM ASM code, arm-elf-assembler included.	zero_gravity	4773d 08h	/storm_core/
9	documentation updated	zero_gravity	4863d 06h	/storm_core/
8	documentation uploaded ;)	zero_gravity	4865d 00h	/storm_core/
7	- new register file architecture - fixed multi-cycle op bug - architecture update	zero_gravity	4868d 23h	/storm_core/
6	new core version - now with arm compatible memory interface	zero_gravity	4874d 23h	/storm_core/
5	memory interface updated	zero_gravity	4925d 22h	/storm_core/
4	new instruction cycle controller - interrupt call bug seems to be fixed	zero_gravity	4928d 00h	/storm_core/
3		zero_gravity	4929d 07h	/storm_core/
2		zero_gravity	4941d 08h	/storm_core/
1	The project and the structure was created	root	4944d 15h	/storm_core/