OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 101

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 Absolute indirect addressing mode is coded and simulated. creep 5667d 08h /t6507lp/trunk/rtl/verilog/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5667d 09h /t6507lp/trunk/rtl/verilog/
99 Only Package.v should be used. creep 5667d 09h /t6507lp/trunk/rtl/verilog/
98 Updated status and some comments. creep 5667d 09h /t6507lp/trunk/rtl/verilog/
97 Removed obsolete TODO. creep 5667d 09h /t6507lp/trunk/rtl/verilog/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5670d 01h /t6507lp/trunk/rtl/verilog/
95 IDX addressing mode is also 100%, coded and simulated. creep 5670d 05h /t6507lp/trunk/rtl/verilog/
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5671d 01h /t6507lp/trunk/rtl/verilog/
93 Opcode for BNE was wrong. creep 5671d 03h /t6507lp/trunk/rtl/verilog/
92 Absolute indexed mode working properly. All cases were simulated. creep 5671d 07h /t6507lp/trunk/rtl/verilog/
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5671d 08h /t6507lp/trunk/rtl/verilog/
90 CMP, CPX and CPY affect carry flag (in this case it indicates a borrow) but they don't affect overflow. gabrieloshiro 5671d 08h /t6507lp/trunk/rtl/verilog/
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 5671d 08h /t6507lp/trunk/rtl/verilog/
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5671d 09h /t6507lp/trunk/rtl/verilog/
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5672d 00h /t6507lp/trunk/rtl/verilog/
86 Zero page indexed mode is working fine. creep 5672d 04h /t6507lp/trunk/rtl/verilog/
85 alu_x and alu_y variables created. gabrieloshiro 5672d 09h /t6507lp/trunk/rtl/verilog/
84 X and Y register are passed from ALU to FSM. gabrieloshiro 5672d 09h /t6507lp/trunk/rtl/verilog/
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5672d 09h /t6507lp/trunk/rtl/verilog/
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5673d 01h /t6507lp/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.