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[/] [uart16550/] [tags/] [rel_3/] [rtl/] - Rev 73

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Rev	Log message	Author	Age	Path
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8268d 03h	/uart16550/tags/rel_3/rtl/
71	Removed confusing comment	gorban	8292d 23h	/uart16550/tags/rel_3/rtl/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8298d 08h	/uart16550/tags/rel_3/rtl/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8306d 23h	/uart16550/tags/rel_3/rtl/
68	lsr[7] was not showing overrun errors.	mohor	8310d 06h	/uart16550/tags/rel_3/rtl/
67	Missing declaration of rf_push_q fixed.	mohor	8317d 06h	/uart16550/tags/rel_3/rtl/
66	rx push changed to be only one cycle wide.	mohor	8317d 06h	/uart16550/tags/rel_3/rtl/
65	Warnings fixed (unused signals removed).	mohor	8318d 11h	/uart16550/tags/rel_3/rtl/
64	Warnings cleared.	mohor	8318d 11h	/uart16550/tags/rel_3/rtl/
63	Synplicity was having troubles with the comment.	mohor	8318d 12h	/uart16550/tags/rel_3/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8319d 10h	/uart16550/tags/rel_3/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8320d 04h	/uart16550/tags/rel_3/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8320d 09h	/uart16550/tags/rel_3/rtl/
59	MSR register fixed.	mohor	8323d 06h	/uart16550/tags/rel_3/rtl/
58	After reset modem status register MSR should be reset.	mohor	8323d 09h	/uart16550/tags/rel_3/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8324d 09h	/uart16550/tags/rel_3/rtl/
56	thre irq should be cleared only when being source of interrupt.	mohor	8324d 09h	/uart16550/tags/rel_3/rtl/
55	some synthesis bugs fixed	gorban	8324d 21h	/uart16550/tags/rel_3/rtl/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8325d 10h	/uart16550/tags/rel_3/rtl/
53	Scratch register define added.	mohor	8326d 10h	/uart16550/tags/rel_3/rtl/

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Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [rtl/] - Rev 73

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