OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] - Rev 70

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8298d 04h /uart16550/trunk/rtl/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8306d 19h /uart16550/trunk/rtl/
68 lsr[7] was not showing overrun errors. mohor 8310d 03h /uart16550/trunk/rtl/
67 Missing declaration of rf_push_q fixed. mohor 8317d 02h /uart16550/trunk/rtl/
66 rx push changed to be only one cycle wide. mohor 8317d 03h /uart16550/trunk/rtl/
65 Warnings fixed (unused signals removed). mohor 8318d 07h /uart16550/trunk/rtl/
64 Warnings cleared. mohor 8318d 08h /uart16550/trunk/rtl/
63 Synplicity was having troubles with the comment. mohor 8318d 08h /uart16550/trunk/rtl/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8319d 07h /uart16550/trunk/rtl/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8320d 01h /uart16550/trunk/rtl/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8320d 06h /uart16550/trunk/rtl/
59 MSR register fixed. mohor 8323d 03h /uart16550/trunk/rtl/
58 After reset modem status register MSR should be reset. mohor 8323d 06h /uart16550/trunk/rtl/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8324d 05h /uart16550/trunk/rtl/
56 thre irq should be cleared only when being source of interrupt. mohor 8324d 06h /uart16550/trunk/rtl/
55 some synthesis bugs fixed gorban 8324d 18h /uart16550/trunk/rtl/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8325d 07h /uart16550/trunk/rtl/
53 Scratch register define added. mohor 8326d 07h /uart16550/trunk/rtl/
52 Scratch register added gorban 8326d 20h /uart16550/trunk/rtl/
51 Igor fixed break condition bugs gorban 8326d 20h /uart16550/trunk/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.