OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 26

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
21 Added timeout, total error count, and XGCHN test rehayes 5441d 10h /xgate/trunk/bench/verilog/
20 Added event signal for compare error tracking in top level test bench. rehayes 5441d 10h /xgate/trunk/bench/verilog/
19 Verilog memory image for testing rehayes 5441d 10h /xgate/trunk/bench/verilog/
11 Update with Single Step debuging test rehayes 5455d 10h /xgate/trunk/bench/verilog/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5468d 10h /xgate/trunk/bench/verilog/
2 Initial Checkin rehayes 5476d 08h /xgate/trunk/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.