URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 81

Rev	Log message	Author	Age	Path
81	initial import	simont	7928d 03h	/
80	removing unused modules	simont	7928d 03h	/
79	initial import	simont	7928d 04h	/
78	alu with registered outputs	simont	7988d 03h	/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7997d 00h	/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7997d 00h	/
75	initial import	simont	7997d 00h	/
74	add module oc8051_wb_iinterface	simont	8005d 01h	/
73	initial import	simont	8005d 01h	/
72	fix bug in interface to external data ram	simont	8005d 03h	/
71	add cache	simont	8009d 02h	/
70	initial import	simont	8009d 02h	/
69	add parameters	simont	8009d 04h	/
68	add instruction cache and DELAY parameters for external ram, rom	simont	8009d 04h	/
67	add parameters for instruction cache	simont	8009d 04h	/
66	added xrom_test	simont	8010d 01h	/
65	add oc8051_icache and oc8051_cache_ram	simont	8010d 01h	/
64	signal es_int=1'b0	simont	8010d 01h	/
63	initial import	simont	8010d 01h	/
62	fix bugs in instruction interface	simont	8010d 01h	/