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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

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Rev Log message Author Age Path
91 *** empty log message *** simont 7906d 03h /
90 change module name. simont 7910d 20h /
89 Replaced oc8051_ram by generic_dpram. rherveille 7972d 00h /
88 fix bugs simont 7977d 00h /
87 add include oc8051_defines.v simont 7977d 00h /
86 initial input simont 7977d 00h /
85 prepare bugs simont 7977d 00h /
84 remove wb_bus_mon simont 7985d 00h /
83 replace some modules simont 7985d 00h /
82 replace some modules simont 7985d 00h /
81 initial import simont 7985d 00h /
80 removing unused modules simont 7985d 00h /
79 initial import simont 7985d 00h /
78 alu with registered outputs simont 8045d 00h /
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 8053d 21h /
76 add module oc8051_sfr, 256 bytes internal ram simont 8053d 21h /
75 initial import simont 8053d 21h /
74 add module oc8051_wb_iinterface simont 8061d 21h /
73 initial import simont 8061d 21h /
72 fix bug in interface to external data ram simont 8061d 23h /

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