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Rev Log message Author Age Path
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6450d 08h /
19 Added initial unified memory core. sybreon 6451d 22h /
18 Moved testbench into /sim/verilog.
Simulation cleanups.
sybreon 6452d 15h /
17 Cosmetic changes sybreon 6453d 19h /
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.
sybreon 6454d 07h /
15 Removed ROM file. Please generate it from the SW directory. sybreon 6460d 21h /
14 Added initial interrupt/exception support. sybreon 6460d 21h /
13 Fibonacci rom sybreon 6461d 05h /
12 Minor changes sybreon 6461d 05h /
11 Removed unused signals sybreon 6461d 05h /
10 Fixed minor bugs sybreon 6461d 05h /
9 Extended testbench code sybreon 6461d 05h /
8 Fixed memory read-write data hazard sybreon 6461d 05h /
7 Added CMP instruction sybreon 6461d 05h /
6 Fixed C code bug which passes the test sybreon 6461d 05h /
5 Fixed endian correction issues on data bus. sybreon 6461d 20h /
4 Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee. sybreon 6469d 23h /
3 initial import sybreon 6486d 17h /
2 initial import sybreon 6486d 17h /
1 Standard project directories initialized by cvs2svn. 6486d 17h /

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