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58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4594d 14h /
57 Added parameters of frame header constants for packet parsing. edn_walter 4594d 15h /
56 Added parameter of VLAN TPID for stacked VLAN parsing. edn_walter 4594d 15h /
55 Updated the SOPC Builder example with GMII/MII support. edn_walter 4595d 12h /
54 Added support for MII interface as well as GMII interface. Updated unit and top-level test cases. edn_walter 4595d 12h /
53 Corrected 2 bugs: SOPC addressing and Wrong Preamble+SFD format. edn_walter 4597d 10h /
52 1. Corrected GMII BFM preamble+sfd size error: 4B 5555555d changed to 8B 5555555555555555d5.
2. Corrected packet parser 4B counter accordingly.
edn_walter 4597d 10h /
51 Making test case pass for SOPC simulation. edn_walter 4601d 21h /
50 Added missing simulation library. edn_walter 4601d 22h /
49 Added missing simulation library. edn_walter 4602d 06h /
48 1. Added testbench for SOPC Builder example. Need to fully implement the self-check test cases. Just ignore the reported failures, and check the waveform for correct addressing.
2. Added GENERATE BLOCK for top-level addr_in unit selection. In normal top-level instantiation without modify the default addr_is_in_word = 0 parameter, the default address unit is in byte (8bit); When instantiated in SOPC Builder, the address unit is default to word (32bit).
edn_walter 4602d 10h /
47 Added test case of -16 negative period_adj value, to show the effect trying to set time backwards. Thanks to Frank Yang's question. edn_walter 4602d 21h /
46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4605d 12h /
45 1. optimized area, by removing unused registers.
2. optimized timing, by removing latches.
edn_walter 4606d 03h /
44 Updated TSU testbench. edn_walter 4606d 06h /
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4607d 04h /
42 Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. edn_walter 4607d 10h /
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4607d 12h /
40 Release version 1.1 edn_walter 4607d 15h /
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.
edn_walter 4607d 15h /

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