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Rev Log message Author Age Path
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4915d 00h /
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4915d 15h /
120 Updated main package with lots of wait states for all areas ja_rd 4924d 18h /
119 Updated pre-generated simulation and synthesis demos ja_rd 4924d 18h /
118 Updates sim scripts to include new cache ja_rd 4924d 18h /
117 Updated project doc (still not fully up to date) ja_rd 4924d 18h /
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic		 ja_rd 4924d 19h /
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)		 ja_rd 4924d 21h /
114 ADDED: 1st version of real cache ja_rd 4924d 21h /
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)		 ja_rd 4924d 23h /
112 Updated simulation package for compatibility to new cache ja_rd 4924d 23h /
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4924d 23h /
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4924d 23h /
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation		 ja_rd 4924d 23h /
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)		 ja_rd 4924d 23h /
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code		 ja_rd 4928d 21h /
106 SW samples updated:
- Added batch files for running the SW simulation		 ja_rd 4928d 22h /
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux		 ja_rd 4928d 22h /
104 FIXED typo in last commit for simulation template ja_rd 4933d 13h /
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4933d 13h /

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