OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] - Rev 146

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
146 Added D-Cache setup code to 'adventure' bootstrap code
(redundant since common C startup code already does it but...)		 ja_rd 4927d 13h /
145 MAJOR UPDATE: first version of D-Cache ja_rd 4927d 13h /
144 Added cache setup code to common startup code
Important: the new cache won't work without this		 ja_rd 4927d 13h /
143 'adventure' sample by default will log from 0xb0000000
and simulation length is now longer		 ja_rd 4929d 03h /
142 'Adventure' bootstrap code now enables the cache
(and runs noticeably faster on DE-1 board)		 ja_rd 4929d 03h /
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled		 ja_rd 4929d 03h /
140 BUG FIX in cpu: MTCx was using Rs as source instead of Rt
BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong		 ja_rd 4929d 03h /
139 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4929d 21h /
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4929d 21h /
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4929d 21h /
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4929d 21h /
135 Added debug output to synthesizable MPU template. ja_rd 4929d 21h /
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4929d 21h /
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4932d 18h /
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4932d 18h /
131 change to local system-dependent directory path ja_rd 4932d 18h /
130 typo fix ja_rd 4932d 18h /
129 updated pregenerated demo ('hello') ja_rd 4932d 18h /
128 updated precompiled simulation testbench ja_rd 4932d 19h /
127 added SDRAM verilog simulation model to sim script ja_rd 4932d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.