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Rev Log message Author Age Path
50 Updated the CPU and distribution in general to handle 8-bit bytes. dgisselq 2835d 10h /
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2959d 23h /
48 Greatly expanded the specification, including how to's, getting started guide,
register definitions, etc.		 dgisselq 2962d 12h /
47 Updated. dgisselq 2980d 03h /
46 Sped the UART simulator back up to 1MBaud. dgisselq 2980d 03h /
45 Updated the flash, and the flash test bench, for Quad I/O read commands. dgisselq 2980d 03h /
44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.		 dgisselq 2980d 03h /
43 Cleaned up the CPU memory documentation. dgisselq 2980d 03h /
42 Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test.		 dgisselq 2980d 03h /
41 Added the CPU test program to the Arty distribution. This works. dgisselq 2980d 03h /
40 Fixed a problem with the declaration of variables to be volatile. dgisselq 2980d 03h /
39 Fixes the OLED test so that it runs using the DMA. dgisselq 2980d 03h /
38 ZipLoad can now load programs to non-reset locations. dgisselq 2980d 03h /
37 Updated documentation and copyright. dgisselq 2980d 03h /
36 Lots of changes, see the git changelog for details. dgisselq 2986d 13h /
35 Added comments and copyright notice. dgisselq 2990d 00h /
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2990d 02h /
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2995d 08h /
32 Brought the CPU to its first working version, to include demo. dgisselq 2996d 11h /
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2997d 04h /

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