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Rev Log message Author Age Path
131 This brings the OpenRISC repository for GDB 6.8 into line with the patched
tool which is distributed. Missing Makefile.in and configure files are added.
jeremybennett 5272d 04h /
130 Updating uclibc patch julius 5273d 07h /
129 Previous commit was before saving file. jeremybennett 5274d 03h /
128 Tagging the 0.4.0rc2 candidate release of Or1ksim jeremybennett 5274d 03h /
127 New config option to allow l.xori with unsigned operand. jeremybennett 5274d 04h /
126 More explanation of l.xori. jeremybennett 5274d 04h /
125 Update to specification of l.xori. jeremybennett 5274d 11h /
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5274d 23h /
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5275d 03h /
122 Added l.ror and l.rori with associated tests. jeremybennett 5275d 23h /
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5276d 00h /
120 Documents exception generation by l.jalr and l.jr jeremybennett 5276d 00h /
119 Updated to clarify exceptions for division and details of multiplication. jeremybennett 5276d 12h /
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5276d 21h /
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5279d 00h /
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5279d 00h /
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5280d 00h /
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5280d 01h /
113 Updates to exception handling for l.add and l.div jeremybennett 5280d 23h /
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5281d 00h /

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