OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 457

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5081d 02h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 5081d 03h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 5085d 05h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 5087d 07h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 5087d 18h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 5088d 02h /
451 More tidying up. jeremybennett 5091d 22h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5092d 02h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5093d 23h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 5094d 09h /
447 Updates to register order. jeremybennett 5095d 02h /
446 gdb-7.2 gdbserver updates. julius 5095d 21h /
445 gdbserver update to use kernel port ptrace register definitions. julius 5096d 18h /
444 Changes to ABI handling of varargs. jeremybennett 5097d 03h /
443 Work in progress on more efficient Ethernet. jeremybennett 5097d 06h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5097d 21h /
441 Changes for gdbserver. jeremybennett 5098d 03h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 5098d 22h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5101d 02h /
438 Fix to newlib header and library locations. jeremybennett 5104d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.