URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] - Rev 797

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Rev	Log message	Author	Age	Path
797	Changed hardcoded address for fake MC to use a define.	lampret	8292d 12h	/
796	Removed unused ports wb_clki and wb_rst_i	lampret	8292d 12h	/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8292d 16h	/
794	Added again just recently removed full_case directive	lampret	8292d 17h	/
793	Added synthesis off/on for timescale.v included file.	lampret	8292d 17h	/
792	Fixed port names that changed.	lampret	8292d 17h	/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8292d 17h	/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8292d 17h	/
789	Added response from memory controller (addr 0x60000000)	lampret	8292d 17h	/
788	Some of the warnings fixed.	lampret	8292d 18h	/
787	Added romfs.tgz	lampret	8293d 12h	/
786	Moved UCF constraint file to the backend directory.	lampret	8293d 12h	/
785	Added XSV specific documentation.	lampret	8293d 12h	/
784	Added soem missing files.	lampret	8293d 12h	/
783	Added sim directory and sub files/dirs.	lampret	8293d 12h	/
782	Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory.	lampret	8293d 12h	/
781	Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well.	lampret	8293d 13h	/
780	Added libraries.	lampret	8293d 13h	/
779	Added bench directory	lampret	8293d 13h	/
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8293d 14h	/

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[/] - Rev 797

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