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Rev Log message Author Age Path
13 Update to rev 0.3, added SINGLE_CYCLE parameter rehayes 5669d 20h /
12 Fixed for single cycle reads rehayes 5670d 15h /
11 Changed read task to capture data at rising edge of clock rehayes 5670d 15h /
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5671d 18h /
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5677d 12h /
8 Fix ack signal in testbench rehayes 5677d 12h /
7 Reflection of minor corrections rehayes 5681d 18h /
6 Reflection of minor corrections rehayes 5681d 18h /
5 rehayes 5719d 14h /
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5719d 14h /
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5719d 15h /
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5719d 15h /
1 The project was created and the structure was created root 5720d 06h /

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