URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 25

Rev	Log message	Author	Age	Path
25	updated for ubuntu 10.4 install	jt_eaton	5322d 11h	/
24	moved to docs	jt_eaton	5323d 14h	/
23	fixed typos and ommisions	jt_eaton	5323d 14h	/
22	added install instructions for ubuntu 10.4	jt_eaton	5323d 15h	/
21	now use serial_rcvr	jt_eaton	5324d 04h	/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5324d 04h	/
19	added serial_xmit module updated and added docs	jt_eaton	5331d 10h	/
18	added geda support files and docs	jt_eaton	5336d 09h	/
17	removed old doc files	jt_eaton	5338d 10h	/
16	added geda scripts and symbols/sch	jt_eaton	5338d 10h	/
15	added io_module with ps2 and uart added soc_mouse with uart and mouse interface fixed latch in mrisc	jt_eaton	5344d 13h	/
14	add web_uploads	jt_eaton	5354d 17h	/
13	updated for xilinx webpack 11.1	jt_eaton	5362d 07h	/
12	switched Makefile to use xilinx 11.1 ise removed timescale from synthesis files now use consist timescale header in all sims	jt_eaton	5362d 18h	/
11	moved bsdl files renamed ucf file	jt_eaton	5368d 13h	/
10	added impact_bat to generate svf files	jt_eaton	5368d 15h	/
9	updated build_cmp and cleaned up fpga script added more utility tools	jt_eaton	5370d 15h	/
8	fixed loop sim, now pick up ROM_WORDS from sw dir	jt_eaton	5372d 15h	/
7	changed loop to use subroutines fixed typo on variants name	jt_eaton	5373d 15h	/
6	added pic_micro from minirisc project with design to run code on a digilent Basys board	jt_eaton	5377d 11h	/