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Rev Log message Author Age Path
37 Hacked a bug fix - probably due to DCache bugs which are due to be fixed - dhrystone-icdc test still does not complete julius 5689d 02h /
36 Couple of makefile updates julius 5689d 05h /
35 Fixed or1200_defines confusion julius 5689d 05h /
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5689d 06h /
33 Fixed up software linker script, and changed placement of vectors where necessary. Icarus tests up to mul-nocache-O2 works but had to re-enable MAC in or1200 julius 5690d 18h /
32 Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim julius 5690d 22h /
31 Further progress with orpsoc test setup julius 5690d 22h /
30 Updating bench julius 5693d 03h /
29 Fixed address decode on 64bit platforms julius 5693d 08h /
28 Added branch and jump relative calculations in or32 idecode tool julius 5693d 08h /
27 Adding OpenRISC instruction decode tool code julius 5693d 10h /
26 Adding testbench and makefile update julius 5694d 08h /
25 Adding sw dir PROPERLY julius 5694d 09h /
24 Attempting to put in sw dir properly julius 5694d 09h /
23 adding sw directory julius 5694d 09h /
22 compiles with icarus. basic make script done julius 5694d 09h /
21 missing file unneback 5694d 10h /
20 wishbone arbiter unneback 5695d 07h /
19 the rest of the design unneback 5695d 08h /
18 the rest of the design unneback 5695d 08h /

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