OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] - Rev 49

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
49 Verilator model now builds OK. julius 5675d 20h /
48 Closer to working verilator build julius 5676d 12h /
47 Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly julius 5676d 16h /
46 Flash memory now also disabled when SDRAM disabled, which is by default. Ethernet now enabled by defining USE_ETHERNET, otherwise it is disabled by default. Default icarus tests now very fast due to this julius 5677d 20h /
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5678d 13h /
44 Beginnings of verilator build - much still to do but the design can now at least be verilated julius 5684d 16h /
43 Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works julius 5684d 21h /
42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 5685d 12h /
41 Removed duplicate or1200_defines.v and timescale.v files julius 5685d 14h /
40 Change name of file and module of orpsoc_top module julius 5685d 15h /
39 Removed auto logging of processor state, added option to enable it in makefile, documented way the tests are done in makefile and that should probably be moved to some readme at some point julius 5685d 16h /
38 Actually that last fix caused another bug. This, and the original, are now fixed. Dhrystone ICDC passes julius 5685d 19h /
37 Hacked a bug fix - probably due to DCache bugs which are due to be fixed - dhrystone-icdc test still does not complete julius 5686d 15h /
36 Couple of makefile updates julius 5686d 18h /
35 Fixed or1200_defines confusion julius 5686d 18h /
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5686d 19h /
33 Fixed up software linker script, and changed placement of vectors where necessary. Icarus tests up to mul-nocache-O2 works but had to re-enable MAC in or1200 julius 5688d 07h /
32 Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim julius 5688d 11h /
31 Further progress with orpsoc test setup julius 5688d 11h /
30 Updating bench julius 5690d 16h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.