OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 A better explanation at top of main sim makefile julius 5672d 01h /
56 OR1k sim tests now implemented and working julius 5672d 01h /
55 Systemc vcd file name based on test name which is passed via command line when the executable is run julius 5672d 03h /
54 Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at julius 5672d 04h /
53 verilator test loop in makefile - same results as icarus julius 5672d 18h /
52 Enabled own printf function using UART as output julius 5672d 18h /
51 Added SystemC Uart model julius 5675d 08h /
50 Tracing enabled on Verilator model julius 5675d 22h /
49 Verilator model now builds OK. julius 5676d 06h /
48 Closer to working verilator build julius 5676d 22h /
47 Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly julius 5677d 02h /
46 Flash memory now also disabled when SDRAM disabled, which is by default. Ethernet now enabled by defining USE_ETHERNET, otherwise it is disabled by default. Default icarus tests now very fast due to this julius 5678d 06h /
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5678d 23h /
44 Beginnings of verilator build - much still to do but the design can now at least be verilated julius 5685d 02h /
43 Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works julius 5685d 07h /
42 Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it. julius 5685d 22h /
41 Removed duplicate or1200_defines.v and timescale.v files julius 5686d 01h /
40 Change name of file and module of orpsoc_top module julius 5686d 01h /
39 Removed auto logging of processor state, added option to enable it in makefile, documented way the tests are done in makefile and that should probably be moved to some readme at some point julius 5686d 03h /
38 Actually that last fix caused another bug. This, and the original, are now fixed. Dhrystone ICDC passes julius 5686d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.