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Rev Log message Author Age Path
173 Adding file top.v diegovalverde 4823d 19h /
172 Modifying to use new testbed by default diegovalverde 4823d 19h /
171 Added TestBench_verilator.cpp and TestBench_verilog.v diegovalverde 4823d 19h /
170 diegovalverde 4827d 12h /
169 Adding scripts folder diegovalverde 4830d 06h /
168 Addign example files diegovalverde 4830d 06h /
167 Added variables to add generic number of cores diegovalverde 4830d 06h /
166 diegovalverde 4830d 06h /
165 No log files shall be created by defualt diegovalverde 4831d 10h /
164 Getting rid of warnings diegovalverde 4832d 05h /
163 Moved this to the simulation folder diegovalverde 4838d 08h /
162 Adding modified Makefile diegovalverde 4838d 08h /
161 diegovalverde 4838d 08h /
160 Adding testbench folder diegovalverde 4839d 09h /
159 Adding makefile diegovalverde 4839d 09h /
158 Adding source code that icarus likes. diegovalverde 4839d 09h /
157 Adding a project that correctly simulates using Icarus verilog diegovalverde 4839d 09h /
156 Cosmetic change diegovalverde 4848d 08h /
155 renaming folder diegovalverde 4848d 08h /
154 Renaming folder to RTL, now all files in a flat structure. diegovalverde 4848d 08h /

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