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Rev Log message Author Age Path
27 initial commit, dual way simplex FIFO unneback 5237d 15h /
26 added ACTEL synthesis directive as define, +ACTEL unneback 5237d 15h /
25 DFF SR as separate logic unneback 5377d 11h /
24 updated fifo interfaces with re/rd and we/wr unneback 5378d 01h /
23 unneback 5380d 14h /
22 async fifo with multiple queues unneback 5380d 14h /
21 added DFF SR unneback 5394d 12h /
20 unneback 5394d 19h /
19 DFF with async clear and set for Altera cycloneIV unneback 5396d 01h /
18 ADDR and DATA width set to 8 resp 32 unneback 5396d 15h /
17 based on updated versatile counter unneback 5400d 13h /
16 changed power of two style unneback 5663d 23h /
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5667d 17h /
14 added PDF unneback 5711d 23h /
13 adr update unneback 5713d 02h /
12 no mux on dual port mem read unneback 5725d 19h /
11 name conflict
wptr1 changed to wptr1_cnt etc
unneback 5725d 21h /
10 rptr2 unneback 5725d 23h /
9 unneback 5731d 18h /
8 unneback 5731d 18h /

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