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Rev Log message Author Age Path
89 Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done.		 dgisselq 3091d 14h /
88 Adjusted copyright date. dgisselq 3091d 14h /
87 Placed the interrupt into the carry chain for less logic area. dgisselq 3091d 14h /
86 Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth.		 dgisselq 3091d 14h /
85 First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.)		 dgisselq 3095d 11h /
84 First part of switching to proper sdspi.v, and not just the link. dgisselq 3095d 11h /
83 Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port.		 dgisselq 3096d 15h /
82 dgisselq 3097d 10h /
81 Adds register values for the SD-Card registers. dgisselq 3097d 10h /
80 Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested).		 dgisselq 3097d 10h /
79 Adds 'bench' and 'sw' targets, and automatically builds them (now). dgisselq 3097d 10h /
78 Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result.		 dgisselq 3097d 10h /
77 Adds register names and values for the SD card interface. dgisselq 3097d 10h /
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.		 dgisselq 3097d 10h /
75 Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.)		 dgisselq 3097d 10h /
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 3097d 10h /
73 Simplified logic. dgisselq 3097d 10h /
72 Sets XULA25 as the default. dgisselq 3097d 11h /
71 Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more.		 dgisselq 3097d 11h /
70 Cosmetic (minor) update. dgisselq 3097d 11h /

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