URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5680d 19h	/8051/trunk/rtl/verilog/oc8051_ports.v
185		root	5736d 20h	/8051/trunk/rtl/verilog/oc8051_ports.v
179	add /* synopsys xx_case */ to case statments.	simont	7815d 14h	/8051/trunk/rtl/verilog/oc8051_ports.v
120	defines for pherypherals added	simont	7897d 22h	/8051/trunk/rtl/verilog/oc8051_ports.v
116	change sfr's interface.	simont	7900d 20h	/8051/trunk/rtl/verilog/oc8051_ports.v
82	replace some modules	simont	7984d 20h	/8051/trunk/rtl/verilog/oc8051_ports.v
46	prepared header	simont	8089d 17h	/8051/trunk/rtl/verilog/oc8051_ports.v
22	fix some bugs	simont	8129d 15h	/8051/trunk/rtl/verilog/oc8051_ports.v
15	commbinatorial loop removed	simont	8133d 21h	/8051/trunk/rtl/verilog/oc8051_ports.v
5	more linter corrections; 2 tests still fail	markom	8136d 22h	/8051/trunk/rtl/verilog/oc8051_ports.v
4	Code repaired to satisfy the linter; testbech fails	markom	8136d 23h	/8051/trunk/rtl/verilog/oc8051_ports.v
2	Initial CVS import	simont	8152d 21h	/8051/trunk/rtl/verilog/oc8051_ports.v