URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5680d 20h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
185		root	5736d 21h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
138	Change buffering to save one clock per instruction.	simont	7872d 19h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
136	registering outputs.	simont	7873d 00h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
127	fix bug (cyc_o and stb_o)	simont	7892d 01h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
110	change adr_i and adr_o length.	simont	7904d 16h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
82	replace some modules	simont	7984d 21h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
73	initial import	simont	8061d 18h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v