URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl/] [ram_16x64.v] - Rev 10

Rev	Log message	Author	Age	Path
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4628d 00h	/aes_highthroughput_lowarea/trunk/verilog/rtl/ram_16x64.v
5	Updating sub-directory structure	motilito	5083d 03h	/aes_highthroughput_lowarea/trunk/verilog/rtl/ram_16x64.v