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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Rev 73

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Rev	Log message	Author	Age	Path
72	Fixed AL generation Added median filter on SDA and SCL inputs	rherveille	5436d 17h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
68	New directory structure.	root	5745d 11h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
67	Fixed slave_wait clocked event syntax	rherveille	5778d 13h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
66	Fixed type iscl_oen instead of scl_oen	rherveille	5793d 12h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5793d 23h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
60	Added missing semicolons ';' on endif	rherveille	6625d 21h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
59	fixed short scl high pulse after clock stretch	rherveille	6630d 22h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7512d 21h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7512d 22h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7583d 01h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
39	Forgot an 'end if' :-/	rherveille	7781d 18h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7785d 02h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7970d 09h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7974d 07h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
31	Core is now a Multimaster I2C controller.	rherveille	8010d 17h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
27	Cleaned up code	rherveille	8036d 11h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	8067d 15h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8205d 01h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8426d 21h	/i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd

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