URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [mips_mpu1_template.vhdl] - Rev 106

Rev	Log message	Author	Age	Path
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4996d 14h	/ion/trunk/src/mips_mpu1_template.vhdl
97	CPU rd and wr data address buses unified	ja_rd	5020d 23h	/ion/trunk/src/mips_mpu1_template.vhdl
87	Added UART RX interface to MPU template	ja_rd	5031d 20h	/ion/trunk/src/mips_mpu1_template.vhdl
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	5041d 17h	/ion/trunk/src/mips_mpu1_template.vhdl
65	Fixed io input mux in MPU template 1	ja_rd	5042d 10h	/ion/trunk/src/mips_mpu1_template.vhdl
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	5043d 23h	/ion/trunk/src/mips_mpu1_template.vhdl
56	synthesis mpu template updated: BRAM is now one 32-bit-wide block instead of 4 8-bitters (it is read only) python script updated accordingly	ja_rd	5044d 12h	/ion/trunk/src/mips_mpu1_template.vhdl
55	First version of cache: stub, 1-word cache (forgot to commit new mpu template file)	ja_rd	5044d 12h	/ion/trunk/src/mips_mpu1_template.vhdl