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[/] [ion/] [trunk/] [src/] [mips_tb2_template.vhdl] - Rev 102

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Rev Log message Author Age Path
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4996d 21h /ion/trunk/src/mips_tb2_template.vhdl
97 CPU rd and wr data address buses unified ja_rd 5021d 06h /ion/trunk/src/mips_tb2_template.vhdl
86 Adapted TB template to use log trigger address ja_rd 5032d 03h /ion/trunk/src/mips_tb2_template.vhdl
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash
ja_rd 5042d 00h /ion/trunk/src/mips_tb2_template.vhdl
74 Fixed (harmless) error in simulation template 2 ja_rd 5042d 04h /ion/trunk/src/mips_tb2_template.vhdl
51 Adapted simulation and synth templates for cache module ja_rd 5044d 23h /ion/trunk/src/mips_tb2_template.vhdl
42 Added cache stub module, plus related test bench ja_rd 5049d 01h /ion/trunk/src/mips_tb2_template.vhdl

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