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[/] [iso7816_3_master/] [trunk/] [sources/] [Uart.v] - Rev 9

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7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional
acapola 5073d 17h /iso7816_3_master/trunk/sources/Uart.v
5 draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself) acapola 5075d 18h /iso7816_3_master/trunk/sources/Uart.v
4 Basic test bench completed for T=0: a card send ATR, reader send a command
TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)
acapola 5076d 18h /iso7816_3_master/trunk/sources/Uart.v
2 acapola 5083d 20h /iso7816_3_master/trunk/sources/Uart.v

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